[FPGA] VGA text mode controller


After I got the RISC processor working I wanted it to do something more visual than writing to an memory mapped 7-segment LED display so I decided to write a VGA controller for it, obviously I didn’t want to have to write a graphics and font library for it so I decided to do a text mode VGA controller rather than a full graphics controller.

I decided to implement it in a very modular way and to start with the low level stuff so I first created a timebase component which would be instantiated twice, once for the horizontal scan and once for the vertical scan, these modules automatically generated both the control signals for blanking, sync generation and in the case of the horizontal instance, the triggering of the vertical timebase. They obviously also generate the current pixel horizontal and vertical position to be used for looking up the pixel value, the pixel value is determined by looking up the character code at the current position and then using a font table to determine whether that pixel should be the background or foreground colour.

The text RAM is write-only from the perspective of the processor, and is implemented through an alterasyncram megafunction, and has a separate clock input for the read and write ports, the read port is obviously clocked from the pixel clock and the write port clock is exposed as a port on the controller function.

The pixel clock is generated through a PLL from a 50MHz input clock and is set to a fixed rate. The VGA controller uses a pixel resolution of 640×400 resulting in a text resolution of 80×25 with its 8×16 font. It supports a 12-bit global background and foreground colour which are at the moment hard-wired but can easily be mapped to an memory address.

Notes

To build this project you either need to edit the project file and connect it to a different bus( although there is a preloaded message in the text RAM, so you could just tie the bus to 0) or download the processor project too and place both the directories in the same parent directory.

This project uses Altera specific megafunctions and must be significantly altered to run on other FPGA’s

This project was tested on an Altera DE-1 FPGA development board, you might need to edit it to work on a different board.

Links

Download source code
The processor it was made for

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