[FPGA] RISC Processor

I designed and implemented this processor for my HAVO (secondary school) final assignment, for which it scored 10 out of 10 points and about which the local university(Universiteit Twente) who helped my school assess it said it would have been usable as a thesis for CS master.

It has 32 general registers and a link register for function returns, it supports direct, indirect and indexed addressing modes and has almost all basic operations implemented as instructions.

I also wrote an assembler for it, which is included in the Google Code project linked to below.

Click here to skip to the links and downloads section



  • Addition
  • Subtraction
  • Multiplication
  • Compare (Subtraction which discards the result but sets the status bits)


  • And
  • Or
  • Exclusive or
  • Not and


  • Load general purpose register
  • Store general purpose register
  • Load special (Link, Control) register
  • Store special (Link, Control) register


All branch (branch, call or return) instructions are conditional (support the conditions listed below) and support both immediate mode and register based relative targets.


  • Branch
  • Call
  • Return


  • Less than
  • Equal
  • Greater than
  • Unconditional


Download most recent source code
GoogleCode project (outdated code)
The paper I wrote about it as part of the assignment (Dutch)
YouTube video of my presentation about the assignment (Dutch)

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